The present invention relates to comparators, in particular for use in analog-to-digital converters such as successive approximation register (SAR) analog-to-digital converters and measures to increase the precision of comparators.
Successive approximation register (SAR) converters for analog-to-digital conversion are used in integrated CMOS devices since they provide a reasonable resolution and conversion time and can be implemented by optimally utilizing the advantages of CMOS technology, for example small-sized switches and capacitors having well-defined relative capacitances.
Although SAR analog-to-digital converters can be implemented in different topologies, they generally include at least one capacitor array with capacitors of different values forming a 2C-C-network or forming a capacitance array network with capacitance values in relation of 2N to one another. The capacitors of the capacitor array can be charged by being connected to an input signal line carrying an input signal potential to be converted. The capacitor array is connected to a latch/comparator which serves for evaluating a potential difference with respect to the potential stored in the capacitor array. The comparison result is subsequently stored in a shift register. Based on the comparison result of the previous sampling phase, the switching of one or more capacitors of the at least one capacitor array is performed to increase or decrease the potential stored in the at least one capacitor array before a next comparison is carried out.
With respect to conversion speed, power consumption and accuracy, the comparator is a critical element of such an analog-to-digital converter. By its evaluation time, the comparator affects the possible accuracy of the SAR analog-to-digital converter at a given conversion speed or the possible conversion speed at a given accuracy, since the comparators are responsible for a significant portion of 30% to 50% of the conversion time.
Furthermore, the comparators of an SAR analog-to-digital converter significantly contribute to the total power consumption of an analog-to-digital converter, for example between 20% and 70%. To evaluate the performance of an analog-to-digital converter, a figure of merit (FOM) has been defined which brings into relation power consumption, accuracy and sampling rate by FOM=P/(2ENOB×fs), whereby P is the power consumption, fs corresponds to the sampling rate and ENOB corresponds to the effective number of bits, i.e. as defined by the signal-to-noise-and-distortion ratio SNDR, as e. g. ENOB=(SNDR−1.76)/6.02. From the above relation it can be seen that in order to correspond to the above scheme and to maintain performance, an increase of performance of an analog-to-digital converter by increasing the comparison speed of the comparators by a factor of 2 does usually not result in an increase of power consumption by more than the factor 2. In practice, however, doubling the comparison speed often results in an increase of power consumption by a factor of 4. The same holds for increasing the conversion accuracy by 1 bit. This leads to a situation where a power-efficient implementation of a high-resolution analog-digital converter usually requires a significantly longer conversion time.